The present application describes systems and techniques relating to first in first out (FIFO) memory design, for example, a FIFO designed to receive data over a bus from interleaved multiple concurrent transactions.
In the field of FIFO memory design, addressing the potential for FIFO overflow and the resulting loss of data is a significant design consideration. One traditional approach is to design the system and/or device in which the FIFO memory is to be placed such that data will always be read out of the FIFO memory faster than the data is written into the FIFO memory.
Other conventional approaches include adding circuitry to the FIFO memory to output information relating to the current state of the FIFO memory. This information can then be used by external components in orchestrating data writing and reading, into and out of the FIFO memory. Typical examples of such FIFO state outputs include a full flag, an empty flag, an almost full flag and an almost empty flag. Additionally, some FIFO memories include circuitry that makes the almost full flag and/or the almost empty flag programmable.